View LTC3421_5671617.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc3122 1 3122f typical a pplica t ion fea t ures descrip t ion 15v, 2.5a synchronous step-up dc/dc converter with output disconnect the ltc ? 3122 is a synchronous step-up dc/dc converter with true output disconnect and inrush current limiting. the 2.5a current limit along with the ability to program output voltages up to 15v makes the ltc3122 well suited for a variety of demanding applications. once started, opera- tion will continue with inputs down to 500mv, extending runtime in many applications. the ltc3122 features output disconnect in shutdown, dramatically reducing input power drain and enabling v out to completely discharge. adjustable pwm switching from 100khz to 3mhz optimizes applications for highest efficiency or smallest solution footprint. the oscillator can also be synchronized to an external clock for noise sensitive applications. selectable burst mode operation reduces quiescent current to 25a, ensuring high efficiency across the entire load range. an internal soft-start limits inrush current during start-up. other features include a <1a shutdown current and ro - bust protection under short-circuit, thermal overload, and output overvoltage conditions. the ltc3122 is offered in both a low profile 12-lead (3mm 4mm 0.75 mm) dfn package and a 12-lead thermally enhanced msop package. 5v to 12v synchronous boost converter with output disconnect a pplica t ions n v in range: 1.8v to 5.5v, 500mv after start-up n output voltage range: 2.2v to 15v n 800ma output current for v in = 5v and v out = 12v n output disconnects from input when shut down n synchronous rectification: up to 95% efficiency n inrush current limit n up to 3mhz adjustable switching frequency synchronizable to external clock n selectable burst mode ? operation: 25a i q n output overvoltage protection n soft-start n <1a i q in shutdown n 12-lead, 3mm 4mm 0.75mm thermally enhanced dfn and msop packages n rf power n piezo actuators n small dc motors n 12v analog rail from battery , 5v, or backup capacitor l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. efficiency curve 3122 ta01a v in sd pwm/sync rt v cc v out cap fb v c ltc3122 sgnd pgnd 210k 390pf sw 3.3h 113k 1.02m 10pf 4.7f 100nf 22f v out 12v 800ma 57.6k v in 5v 4.7f onoff pwm burst load current (ma) 0.01 efficiency (%) power loss (w) 100 90 70 50 40 80 60 30 20 10 0 10 1 0.1 0 10 0.1 3122 ta01b 1000 1 100 pwm burst mode operation pwm power loss
ltc3122 2 3122f a bsolu t e maxi m u m r a t ings v in voltage .................................................. C0 .3v to 6v v out voltage ............................................ C0 .3v to 18v sw voltage (note 2) .................................. C 0.3v to 18v sw voltage (pulsed < 100ns) (note 2) ....... C 0.3v to 19v v c , rt voltage .......................................... C0 .3v to v cc (note 1) 12 11 10 9 8 7 13 pgnd 1 2 3 4 5 6 cap v out sgnd sd fb v c sw pgnd v in pwm/sync v cc rt top view de package 12-lead (4mm 3mm) plastic dfn t jmax = 125c, ja = 43c/w (note 5), jc = 5c/w exposed pad (pin 13) is pgnd, must be soldered to pcb for rated thermal performance 1 2 3 4 5 6 sw pgnd v in pwm/sync v cc rt 12 11 10 9 8 7 cap v out sgnd sd fb v c top view 13 pgnd mse package 12-lead plastic msop t jmax = 125c, ja = 40c/w (note 5), jc = 10c/w exposed pad (pin 13) is pgnd, must be soldered to pcb for rated thermal performance p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3122ede#pbf ltc3122ede#trpbf 3122 12-lead (4mm 3mm) plastic dfn C40c to 125c ltc3122ide#pbf ltc3122ide#trpbf 3122 12-lead (4mm 3mm) plastic dfn C40c to 125c ltc3122emse#pbf ltc3122emse#trpbf 3122 12-lead plastic msop C40c to 125c ltc3122imse#pbf ltc3122imse#trpbf 3122 12-lead plastic msop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ cap voltage v out < 5.7v ............................ C 0.3v to (v out + 0.3v) 5.7v v out 11.7 v ...... (v out C 6v) to (v out + 0.3v) v out > 11.7 v ................................. ( v out C 6v) to 12v all other pins ............................................... C 0.3v to 6v operating junction temperature range (notes 3, 4) ............................................ C 40c to 125c storage temperature range .................. C 65c to 150c mse lead temperature (soldering, 10sec) ........... 3 00c
ltc3122 3 3122f e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: voltage transients on the sw pin beyond the dc limit specified in the absolute maximum ratings are non-disruptive to normal operations when using good layout practices, as shown on the demo board or described in the data sheet or application notes. note 3: the ltc3122 is tested under pulsed load conditions such that t a t j . the ltc3122e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3122i is guaranteed the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 3). v in = 3.6v, v out = 12v, rt = 57.6k unless otherwise noted. parameter conditions min. typ max units minimum start-up voltage v out = 0v l 1.7 1.8 v input voltage range after v out 2.2v l 0.5 5.5 v output voltage adjust range l 2.2 15 v feedback voltage l 1.178 1.202 1.225 v feedback input current v fb = 1.4v 1 50 na quiescent current, shutdown v sd = 0v, v out = 0v, not including switch leakage 0.01 1 a quiescent current, active v c = 0v, measured on v in , non-switching 500 700 a quiescent current, burst measured on v in , v fb > 1.4v measured on v out , v fb > 1.4v 25 10 40 20 a a n-channel mosfet switch leakage current v sw = 15v, v out = 15v, v c = 0v 0.1 20 a p-channel mosfet switch leakage current v sw = 0v, v out = 15v, v sd = 0v 0.1 20 a n-channel mosfet switch on-resistance 0.121 p-channel mosfet switch on-resistance 0.188 n-channel mosfet current limit l 2.5 3.5 4.5 a maximum duty cycle v fb = 1.0v l 90 94 % minimum duty cycle v fb = 1.4v l 0 % switching frequency l 0.85 1 1.15 mhz sync frequency range l 0.1 3 mhz pwm/sync input high l 0.9 ?v cc v pwm/sync input low l 0.1?v cc v pwm/sync input current v pwm/sync = 5.5v 0.01 1 a cap clamp voltage v out > 6.1v, referenced to v out C5.2 C5.6 C6.0 v v cc regulation voltage v in < 2.8v, v out > 5v 4 4.25 4.5 v error amplifier transconductance l 70 95 120 s error amplifier output current 25 a soft-start time 10 ms sd input high l 1.6 v sd input low l 0.25 v sd input current v sd = 5.5v 1 2 a to meet specifications over the full C40c to 125c operating junction temperature range. the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) according to the formula: t j = t a + (p d ? ja ) where ja is the thermal impedance of the package. note 4: the ltc3122 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature shutdown is active. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. note 5: failure to solder the exposed backside of the package to the pc board ground plane will result in a thermal impedance much higher than the rated package specifications.
ltc3122 4 3122f typical p er f or m ance c harac t eris t ics pwm mode operation load transient response inrush current control feedback vs temperature r ds(on) vs temperature, both nmos and pmos oscillator frequency vs temperature efficiency vs load current, v out = 5v efficiency vs load current, v out = 7.5v efficiency vs load current, v out = 12v configured as front page application unless otherwise specified. 1s/div 3122 g04 v out 20mv/div ac-coupled inductor current 1a/div i load = 200ma 500s/div 3122 g05 v out 500mv/div ac-coupled i out 500ma/div 80ma 80ma 800ma 2ms/div 3122 g06 v out 5v/div sd 5v/div input current 1a/div temperature (c) ?50 change in r ds(on) from 25c (%) 80 60 40 20 0 ?20 ?40 70 110 ?10 3122 g08 30 150 temperature (c) ?60 change in frequency from 25c (%) 1.0 0.5 ?0.5 ?1.0 0 ?1.5 ?2.0 90 ?10 3122 g09 40 140 temperature (c) ?60 change in v fb from 25c (%) 0.2 0.1 ?0.2 ?0.1 0 ?0.3 ?0.4 ?0.5 ?0.6 40 90 ?10 3122 g07 140 load current (ma) 0.01 efficiency (%) 100 90 70 50 40 80 60 30 20 10 0 10 0.1 3122 g01 10000 1 100 1000 burst pwm v in = 4.2v v in = 3.3v v in = 0.6v load current (ma) 0.01 efficiency (%) 100 90 70 50 40 80 60 30 20 10 0 10 0.1 3122 g03 1000 1 100 pwm v in = 5.4v v in = 4.2v v in = 2.6v burst load current (ma) 0.01 efficiency (%) 100 90 70 50 40 80 60 30 20 10 0 10 0.1 3122 g02 10000 1 100 1000 pwm v in = 5.4v v in = 3.8v v in = 2.3v burst
ltc3122 5 3122f typical p er f or m ance c harac t eris t ics burst mode maximum output current vs v in burst mode i zero current vs v in burst mode quiescent current change vs temperature sd pin threshold frequency vs rt frequency accuracy pwm mode maximum output current vs v in peak current limit change vs temperature pwm operation no load input current vs v in v in (v) 0.5 output current (a) 2.0 1.8 0.8 0.6 0.4 1.6 1.4 1.2 1.0 0.2 0 3.5 4.5 1.5 3122 g10 2.5 5.5 v out = 5v v out = 7.5v v out = 12v v in (v) 0 input current (ma) 70 40 30 20 60 50 10 0 4 5 21 3122 g12 3 6 v out = 5v v out = 7.5v v out = 12v v in , falling (v) 0.5 output current (ma) 350 200 150 100 300 250 50 0 4.5 2.51.5 3122 g13 3.5 5.5 v out = 2.2v v out = 5v v out = 7.5v v out = 12v v in , rising(v) 0.5 i zero current (ma) 140 80 60 40 120 100 20 0 4.5 2.51.5 3122 g14 3.5 5.5 v out = 2.2v v out = 5v v out = 7.5v v out = 12v temperature (c) ?50 change in current from 25c (%) 75 60 45 30 15 0 ?15 70 110 ?10 3122 g14 30 150 temperature (c) ?50 peak current limit change from 25c (%) 2 1 0 ?1 ?2 ?3 ?4 70 110 ?10 3122 g11 30 150 r t (k) 0 frequency (mhz) period (s) 3.0 2.0 1.5 1.0 2.5 0.5 0 12 8 6 4 10 2 0 400 200100 3122 g17 300 600500 frequency period v in falling (v) 0 change in frequency (%) 4 2 1 0 ?1 3 ?2 ?3 ?4 4 21 3122 g18 3 65 v out = 15v v out = 3.6v v out = 2.2v 1s/div 3122 g16 v out 5v/div v sd 500mv/div 900mv 400mv
ltc3122 6 3122f typical p er f or m ance c harac t eris t ics burst mode operation burst mode operation to pwm mode pwm mode to burst mode operation burst mode transient synchronized operation short-circuit response efficiency vs frequency cap pin voltage vs v out v cc vs v in load current (ma) 10 efficiency (%) 100 40 30 20 60 50 70 90 80 10 0 100 3122 g19 1000 f osc = 200khz f osc = 1mhz f osc = 3mhz v out (v) 0 v cap , referred to v out (v) 0 ?3 ?4 ?5 ?2 ?1 ?6 ?7 10 642 3122 g20 8 1412 v in (v) 0 v cc (v) 4.5 4.0 3.5 3.0 2.5 4 21 3122 g21 3 65 v in falling v in rising 1s/div 3122 g26 v sw 5v/div v pwm/sync 5v/div synchronized to 1.3mhz 100s/div 3122 g27 v out 5v/div input current 2a/div short-circuit applied short-circuit removed 20s/div 3122 g23 v out 100mv/div ac-coupled v pwm/sync 2v/div i load = 70ma 20s/div 3122 g24 v out 100mv/div ac-coupled v pwm/sync 2v/div i load = 70ma 5s/div 3122 g22 v out 100mv/div ac-coupled v sw 10v/div inductor current 0.5a/div i load = 50ma 200s/div 3122 g25 v out 200mv/div ac-coupled i load 100ma/div 10ma 10ma 100ma
ltc3122 7 3122f p in func t ions sw (pin 1): switch pin. connect an inductor from this pin to v in . keep pcb trace lengths as short and wide as possible to reduce emi and voltage overshoot. an internal anti-ringing resistor is connected between sw and v in after the inductor current has dropped to near zero, to minimize emi. the anti-ringing resistor is also activated in shutdown and during the sleep periods of burst mode operation. pgnd (pins 2, 13): power ground. when laying out your pcb, provide a short, direct path between pgnd and the output capacitor and tie directly to the ground plane. the exposed pad is ground and must be soldered to the pcb ground plane for rated thermal performance. v in (pin 3): input supply pin. the device is powered from v in unless v out exceeds v in and v in is less than 3v. place a low esr ceramic bypass capacitor of at least 4.7f from v in to pgnd. x5r and x7r dielectrics are preferred for their superior voltage and temperature characteristics. pwm/sync (pin 4): burst mode operation select and oscillator synchronization. do not leave this pin floating. ? pwm/sync = high. disable burst mode operation and maintain low noise, constant frequency operation. ? pwm/sync = low . enable burst mode operation. ? pwm/sync = external clk. the internal oscillator is synchronized to the external clk signal. burst mode operation is disabled. a clock pulse width between 100ns and 2s is required to synchronize the oscillator. an external resistor must be connected between rt and gnd to program the oscillator slightly below the desired synchronization frequency. in non-synchronized applications, repeated clocking of the pwm/sync pin to affect an operating mode change is supported with these restrictions: ? boost mode (v out > v in ): i out <500a: ? pwm/sync 100hz, i out 500a: ? pwm/sync 5khz ? buck mode (v out < v in ): i out <5ma: ? pwm/sync 5hz, i out 5ma: ? pwm/sync 5khz v cc (pin 5): v cc regulator output. connect a low-esr filter capacitor of at least 4.7f from this pin to gnd to provide a regulated rail approximately equal to the lower of v in and 4.25v. when v out is higher than v in , and v in falls below 3v, v cc will regulate to the lower of approximately v out and 4.25v. a uvlo event occurs if v cc drops below 1.6v. switching is inhibited, and a soft-start is initiated when v cc returns above 1.7v. rt (pin 6): frequency adjust pin. connect an external resistor (r t ) from this pin to sgnd to program the oscil - lator frequency according to the formula: r t = 57.6/? osc where ? osc is in mhz and r t is in k. vc (pin 7): error amplifier output. a frequency compen- sation network is connected to this pin to compensate the control loop. see compensating the feedback loop section for guidelines. fb (pin 8): feedback input to the error amplifier. connect the resistor divider tap to this pin. connect the top of the divider to v out and the bottom of the divider to sgnd. the output voltage can be adjusted from 2.2v to 15v ac- cording to this formula: v out = 1.202v ? (1 + r1/r2) sd (pin 9): logic controlled shutdown input. bringing this pin above 1.6v enables normal, free-running operation, forcing this pin below 0.25v shuts the ltc3122 down, with quiescent current below 1a. do not leave this pin floating. sgnd (pin 10): signal ground. when laying out a pc board, provide a short, direct path between sgnd and the (C) side of the output capacitor. v out (pin 11): output voltage sense and the source of the internal synchronous rectifier mosfet. driver bias is derived from v out . connect the output filter capacitor from v out to pgnd, as close to the ic as possible. a minimum value of 10f ceramic is recommended. v out is disconnected from v in when sd is low. cap (pin 12): serves as the low reference for the syn- chronous rectifier gate drive. connect a low esr filter capacitor (typically 100nf) from this pin to v out to provide an elevated ground rail, approximately 5.6v below v out , used to drive the synchronous rectifier.
ltc3122 8 3122f b lock diagra m 3122 bd ltc3122 pwm logic and drivers shutdown sd current sense tsd v ref_up osc sd ovlo anti-ring pwm burst sync control 3 1 l1 11 12 7 8 10 2 13 + ?? + ? adaptive slope compensation i lim ref 4 5 9 ldo v best v in v out 6 oscillator osc + ? bulk control signals soft-start vc clamp sd tsd ovlo reference uvlo thermal sd v ref_up 1.202v tsd sgnd pgnd exposed pad rt v cc v in c in r t sw pwm/sync sd v in 1.8v to 5.5v c vcc 4.7f c out i zero comp ovlo pgnd 16.2v 1.202v g m error amplifier v out cap fb r1 r2 vc c pl v c r pl c1 100nf c c r c c f v out 2.2v to 15v the values of rc, cc, and cf are based upon operating conditions. please refer to compensating the feedback loop section for guidelines to determine optimal values of these components. v in ? +
ltc3122 9 3122f o pera t ion the ltc3122 is an adjustable frequency, 100khz to 3mhz synchronous boost converter housed in either a 12-lead 4mm 3mm dfn or a thermally enhanced msop pack - age. the ltc3122 offers the unique ability to start-up and regulate the output from inputs as low as 1.8v and continue to operate from inputs as low as 0.5v. output voltages can be programmed between 2.2v and 15v. the device also features fixed frequency, current mode pwm control for exceptional line and load regulation. the cur - rent mode architecture with adaptive slope compensation provides excellent transient load response and requires minimal output filtering. an internal 10ms closed loop soft-start simplifies the design process while minimizing the number of external components. with its low r ds(on) and low gate charge internal n-channel mosfet switch and p-channel mosfet synchronous rectifier, the ltc3122 achieves high efficiency over a wide range of load current. high efficiency is achieved at light loads when burst mode operation is commanded. operation can be best understood by referring to the block diagram. l ow v ol tage o pera tion the ltc3122 is designed to allow start-up from input voltages as low as 1.8v . when v out exceeds 2.2v, the ltc3122 continues to regulate its output, even when v in falls to as low as 0.5v. the limiting factors for the applica - tion become the availability of the input source to supply sufficient power to the output at the low voltages, and the maximum duty cycle. note that at low input voltages, small voltage drops due to series resistance become critical and greatly limit the power delivery capability of the converter. this feature extends operating times by maximizing the amount of energy that can be extracted from the input source. l ow n oise f ixed f requency o pera tion soft-start the ltc3122 contains internal cir cuitry to provide closed- loop soft-start operation. the soft-start utilizes a linearly increasing ramp of the error amplifier reference voltage from zero to its nominal value of 1.202v in approximately 10ms, with the internal control loop driving v out from zero to its final programmed value. this limits the inrush current drawn from the input source. as a result, the du - ration of the soft-start is largely unaffected by the size of the output capacitor or the output regulation voltage. the closed loop nature of the soft-start allows the converter to respond to load transients that might occur during the soft-start interval. the soft-start period is reset by a shutdown command on sd, a uvlo event on v cc (v cc < 1.6v), an overvoltage event on v out (v out 16.2v), or an overtemperature event (thermal shutdown is invoked when the die temperature exceeds 170c). upon removal of these fault conditions, the ltc3122 will soft-start the output voltage. error amplifier the non-inverting input of the transconductance error amplifier is internally connected to the 1.202v reference and the inverting input is connected to fb. an external resistive voltage divider from v out to ground programs the output voltage from 2.2v to 15v via fb as shown in figure 1. v out = 1.202v 1 + r1 r2 ? ? ? ? ? ? selecting an r2 value of 121k? to have approximately 10a of bias current in the v out resistor divider yields the formula: r1 = 100.67?(v out C 1.202v) where r1 is in k?. power converter control loop compensation is set by a simple rc network between v c and ground. figure 1. programming the output voltage 3122 f01 fb ltc3122 1.202v r2 r1 v out + ?
ltc3122 10 3122f o pera t ion internal current limit the current limit comparator shuts off the n-channel mosfet switch once its threshold is reached. peak switch current is limited to 3.5a, independent of input or output voltage, except when v out is below 1.5v, resulting in the current limit being approximately half of the nominal peak. lossless current sensing converts the peak current sig - nal of the n-channel mosfet switch into a voltage that is summed with the internal slope compensation. the summed signal is compared to the error amplifier output to provide a peak current control command for the pwm. zero current comparator the zero current comparator monitors the inductor current being delivered to the output and shuts off the synchro- nous rectifier when this current reduces to approximately 50ma. this prevents the inductor current from reversing in polarity, improving efficiency at light loads. oscillator the internal oscillator is programmed to the desired switch - ing frequency with an external resistor from the rt pin to gnd according to the following formula: ? osc (mhz) = 57.6 r t (k ? ) ? ? ? ? ? ? the oscillator also can be synchronized to an external frequency by applying a pulse train to the pwm/sync pin. an external resistor must be connected between rt and gnd to program the oscillator to a frequency approximately 25% below that of the externally applied pulse train used for synchronization. r t is selected in this case according to this formula: r t (k ? ) = 73.2 ? sync (mhz) ? ? ? ? ? ? output disconnect the ltc3122s output disconnect feature eliminates body diode conduction of the internal p-channel mosfet rectifier. this allows for v out to discharge to 0v during shutdown, and draw no current from the input source. it also allows for inrush current limiting at turn-on, minimiz- ing surge currents seen by the input supply. note that to obtain the advantages of output disconnect, there must not be an external schottky diode connected between sw and v out . the output disconnect feature also allows v out to be pulled high, without reverse current being backfed into the power source connected to v in . shutdown the boost converter is disabled by pulling sd below 0.25v and enabled by pulling sd above 1.6v. note that sd can be driven above v in or v out , as long as it is limited to less than the absolute maximum rating. thermal shutdown if the die temperature exceeds 170c typical, the ltc3122 will go into thermal shutdown (tsd). all switches will be turned off until the die temperature drops by approximately 7c, when the device re-initiates a soft-start and switching can resume. boost anti-ringing control the anti-ringing control connects a resistor across the inductor to damp high frequency ringing on the sw pin during discontinuous current mode operation when the inductor current has dropped to near zero. although the ringing of the resonant circuit formed by l and c sw (capacitance on sw pin) is low energy, it can cause emi radiation. v cc regulator an internal low dropout regulator generates the 4.25v (nominal) v cc rail from v in or v out , depending upon operating conditions. v cc is supplied from v in when v in is greater than 3.5v, otherwise the greater of v in and v out is used. the v cc rail powers the internal control circuitry and power mosfet gate drivers of the ltc3122. the v cc regulator is disabled in shutdown to reduce quiescent current and is enabled by forcing the sd pin above its threshold. a 4.7f or larger capacitor must be connected between v cc and sgnd.
ltc3122 11 3122f a pplica t ions i n f or m a t ion overvoltage lockout an overvoltage condition occurs when v out exceeds ap- proximately 16.2v. switching is disabled and the internal soft-start ramp is reset. once v out drops below approxi- mately 15.6v, a soft-start cycle is initiated and switching is enabled. if the boost converter output is lightly loaded so that the time constant product of the output capaci- tance, c out , and the output load resistance, r out is near or greater than the soft-start time of approximately 10ms, the soft-start ramp may end before or soon after switching resumes, defeating the inrush current limiting of the closed loop soft-start following an overvoltage event. short-circuit protection the ltc3122 output disconnect feature allows output short-circuit protection. to reduce power dissipation under overload and short-circuit conditions, the peak switch current limit is reduced to 1.6a. once v out > 1.5v, the current limit is set to its nominal value of 3.5a. v in > v out operation the ltc3122 step-up converter will maintain voltage regu - lation even when the input voltage is above the desired output voltage. note that operating in this mode will exhibit lower efficiency and a reduced output current capability. refer to the typical performance characteristics section for details. burst mode o pera tion when the pwm/sync pin is held low , the boost converter operates in burst mode operation to improve efficiency at light loads and reduce standby current at no load. the input thresholds for this pin are determined relative to v cc with a low being less than 10% of v cc and a high being greater than 90% of v cc . the ltc3122 will operate in fixed frequency pwm mode even if burst mode operation is commanded during soft-start. in burst mode operation, the ltc3122 switches asynchro - nously. the inductor current is first charged to 600ma by turning on the n-channel mosfet switch. once this current threshold is reached, the n-channel is turned off and the p-channel synchronous switch is turned on, de - livering current to the output. when the inductor current discharges to approximately zero, the cycle repeats. in burst mode operation, energy is delivered to the output until the nominal regulation value is reached, at which point the ltc3122 transitions to sleep mode. in sleep, the output switches are turned off and the ltc3122 consumes only 25a of quiescent current. when the output voltage droops approximately 1%, switching resumes. this maxi- mizes efficiency at very light loads by minimizing switching and quiescent losses. output voltage ripple in burst mode operation is typically 1% peak-to-peak. additional output capacitance (10f or greater), or the addition of a small feed-forward capacitor (10pf to 50pf) connected between v out and fb can help further reduce the output ripple. the maximum output current (i out ) capability in burst mode operation varies with v in and v out , as shown in figure 2. figure 2. burst mode maximum output current vs v in v in , falling (v) 0.5 output current (ma) 350 300 200 100 50 250 150 0 3.5 1.5 3122 f02 5.5 2.5 4.5 v out = 2.2v v out = 5v v out = 7.5v v out = 12v
ltc3122 12 3122f a pplica t ions i n f or m a t ion p cb l ayout g uidelines the high switching frequency of the ltc3122 demands careful attention to board layout. a careless layout will result in reduced per formance. maximizing the copper area for ground will help to minimize die temperature rise. a multilayer board with a separate ground plane is ideal, but not absolutely necessary. see figure 3 for an example of a two-layer board layout. rent capability by reducing the inductor ripple current. the minimum inductance value, l, is inversely proportional to operating frequency and is given by the following equation: l > v in ? v out ? v in ( ) ? ? ripple ? v out h and l > 3 ? where: ripple = allowable inductor current ripple (amps peak-to-peak) ? = switching frequency in mhz the inductor current ripple is typically set for 20% to 40% of the maximum inductor current. high frequency ferrite core inductor materials reduce frequency depen- dent power losses compared to cheaper powdered iron types, improving efficiency . the inductor should have low esr (series resistance of the windings) to reduce the i 2 r power losses, and must be able to support the peak inductor current without saturating. molded chokes and some chip inductors usually do not have enough core area to support the peak inductor currents of 3a to 4a seen on the ltc3122. to minimize radiated noise, use a shielded inductor. see table 1 for suggested components and suppliers. table 1. recommended inductors part number value (h) dcr (m) max dc current (a) size (mm) w l h coilcraft lps4018 coilcraft mss7341 coilcraft mss1260t 1 3.3 33 42 20 54.9 3.8 3.72 4.34 4 4 1.8 7.3 7.3 4.1 12.3 12.3 6.2 coiltronics drq73 coiltronics sd7030 coiltronics dr125 0.992 3.3 33 24 24 59 3.99 3 3.84 7.6 7.6 3.55 7 7 3 12.5 12.5 6 murata lqh6pp murata lqh6pp 1 3.3 9 16 4.3 3.8 6 6 4.3 6 6 4.3 sumida cdrh50d28rnp sumida cdrh8d28np sumida cdrh129hf 1.2 3.3 33 13 18 53 4.8 4 4.25 5 5 2.8 8 8 3 12 12 10 taiyo-yuden nr6045 3 31 3.2 6 6 4.5 tdk ltf5022t tdk spm6530t tdk vlf12060t 1.2 3.3 33 25 20 53 4.2 4.1 3.4 5 5.2 2.2 7 7 3.2 11.7 12 6 wrth we-pd 3.3 32.5 3.1 7.3 7.3 2 figure 3. traces carrying high current are direct (pgnd, sw, v in and v out ). trace area at fb and v c are kept low. trace length to input supply should be kept short. v in and v out ceramic capacitors should be placed as close to the ltc3122 pins as possible 12 11 10 9 8 7 13 pgnd 3122 f02 v in pgnd 1 2 3 4 5 6 sgnd fb sw v cc v out pgnd cap v c rt s chottky d iode although it is not required, adding a schottky diode from sw to v out can improve the converter efficiency by about 4%. note that this defeats the output disconnect and short- circuit protection features of the ltc3122. c omponent s election inductor selection the ltc3122 can utilize small sur face mount inductors due to its high switching frequency (up to 3mhz). larger values of inductance will allow slightly greater output cur -
ltc3122 13 3122f a pplica t ions i n f or m a t ion output and input capacitor selection low esr (equivalent series resistance) capacitors should be used to minimize the output voltage ripple. multilayer ceramic capacitors are an excellent choice as they have extremely low esr and are available in small footprints. x5r and x7r dielectric materials are preferred for their ability to maintain capacitance over wide voltage and tem- perature ranges. y5v types should not be used. although ceramic capacitors are recommended, low esr tantalum capacitors may be used as well. when selecting output capacitors, the magnitude of the peak inductor current, together with the ripple voltage specification, determine the choice of the capacitor. both the esr (equivalent series resistance) of the capacitor and the charge stored in the capacitor each cycle contribute to the output voltage ripple. the ripple due to the charge is approximately: v ripple(charge) i p ? v in c out ? v out ? ? where i p is the peak inductor current. the esr of c out is usually the most dominant factor for ripple in most power converters. the ripple due to the capacitor esr is: v ripple(esr) = i load ? r esr ? v out v in where r esr = capacitor equivalent series resistance. the input filter capacitor reduces peak currents drawn from the input source and reduces input switching noise. a low esr bypass capacitor with a value of at least 4.7f should be located as close to the v in pin as possible. low esr and high capacitance are critical to maintain low output voltage ripple. capacitors can be used in parallel for even larger capacitance values and lower effective esr. ceramic capacitors are often utilized in switching converter applications due to their small size, low esr and low leakage currents. however, many ceramic capacitors experience significant loss in capacitance from their rated value with increased dc bias voltage. it is not uncommon for a small surface mount capacitor to lose more than 50% of its rated capacitance when operated near its rated volt- age. as a result it is sometimes necessary to use a larger capacitor value or a capacitor with a larger value and case size, such as 1812 rather than 1206, in order to actually realize the intended capacitance at the full operating volt- age. be sure to consult the vendors curve of capacitance vs dc bias voltage. table 2 shows a sampling of capacitors suited for ltc3122 applications. table 2. representative output capacitors manufacturer, part number value (f) voltage (v) size l w h (mm) type, esr (m) avx, 12103d226mat2a 22 25 3.2 2.5 2.79, x5r ceramic kemet, c2220x226k3ractu 22 25 5.7 5.0 2.4, x7r ceramic kemet, a700d226m016ate030 22 16 7.3 4.3 2.8, alum. polymer, 30m murata, grm32er71e226ke15l 22 25 3.2 2.5 2.5, x7r ceramic nichicon, plv1e121mdl1 82 25 8 8 12, alum. polymer, 25m panasonic, ecj-4yb1e226m 22 25 3.2 2.5 2.5, x5r ceramic sanyo, 25tqc22mv 22 25 7.3 4.3 3.1, poscap, 50m sanyo, 16tqc100m 100 16 7.3 4.3 1.9, poscap, 45m sanyo, 25svpf47m 47 25 6.6 6.6 5.9, os-con, 30m taiyo yuden, tmk325bj226mm-t 22 25 3.2 2.5 2.5, x5r ceramic tdk, ckg57nx5r1e476m 47 25 6.5 5.5 5.5, x5r ceramic cap-xx gs230f 1.2farads 4.5 39 17 3.8 28m cooper a1030-2r5155 1.5farads 2.5 ? = 10, l = 30 60m maxwell bcap0050-p270 50farads 2.5 ? = 18, l = 40 20m for applications requiring a very low profile and very large capacitance, the gs, gs2 and gw series from cap-xx and powerstor aerogel capacitors from cooper all offer very high capacitance and low esr in various low profile packages. a method for improving the converters transient response uses a small feed-forward series network of a capacitor and
ltc3122 14 3122f a resistor across the top resistor of the feedback divider (from v out to fb). this adds a phase-lead zero and pole to the transfer function of the converter as calculated in the compensating the feedback loop section. o pera ting f requency s election there are several considerations in selecting the operating frequency of the converter. t ypically the first consideration is to stay clear of sensitive frequency bands, which cannot tolerate any spectral noise. for example, in products incor - porating rf communications, the 455khz if frequency is sensitive to any noise, therefore switching above 600khz is desired. some communications have sensitivity to 1.1mhz and in that case a 1.5mhz switching converter frequency may be employed. a second consideration is the physical size of the converter. as the operating frequency is increased, the inductor and filter capacitors typically can be reduced in value, leading to smaller sized external components. the smaller solution size is typically traded for efficiency, since the switching losses due to gate charge increase with frequency. another consideration is whether the application can allow pulse-skipping. when the boost converter pulse-skips, the minimum on-time of the converter is unable to support the duty cycle. this results in a low frequency component to the output ripple. in many applications where physical size is the main criterion, running the converter in this mode is acceptable. in applications where it is preferred not to enter this mode, the maximum operating frequency is given by: ? max _ noskip v out ? v in v out ? t on(min) hz where t on(min) = minimum on-time = 100ns. thermal considerations for the ltc3122 to deliver its full power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package. this can be accomplished by taking advantage of the large thermal pad on the un - derside of the ic. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ic and into a copper plane with as much area as possible. if the junction temperature rises above ~170c, the part will go into thermal shutdown, and all switching will stop until the temperature drops approximately 7c. compensating the feedback loop the ltc3122 uses current mode control, with internal adaptive slope compensation. current mode control elimi- nates the second order filter due to the inductor and output capacitor exhibited in voltage mode control, and simplifies the power loop to a single pole filter response. because of this fast current control loop, the power stage of the ic combined with the external inductor can be modeled by a transconductance amplifier g mp and a current controlled current source. figure 4 shows the key equivalent small signal elements of a boost converter. the dc small-signal loop gain of the system shown in figure 4 is given by the following equation: g boost = g ea ? g mp ? g power ? r2 r1 + r2 where g ea is the dc gain of the error amplifier, g mp is the modulator gain, and g power is the inductor current to v out gain. a pplica t ions i n f or m a t ion figure 4. boost converter equivalent model 3122 f04 v out ? + ? + r c v c r o g ma g mp c c c f i l modulator error amplifier 1.202v reference r pl r1 fb r2 r esr r l c pl c out ? i l ? v in 2 ? v out c c : compensation capacitor c out : output capacitor c pl : phase lead capacitor c f : high frequency filter capacitor g ma : transconductance amplifier inside ic g mp : power stage transconductance amplifier r c : compensation resistor r l : output resistance defined as v out /i loadmax r o : output resistance of g ma r pl : phase lead resistor r1, r2: feedback resistor divider network r esr : output capacitor esr : converter efficiency (~90% at higher currents)
ltc3122 15 3122f g ea = g ma ? r o 950v/v (not adjustable; g ma = 95s, r o 10m ? ) g mp = g mp = ? i l ? v c 3.4s (not adjustable) g power = ? v out ? i l = ? v in 2 ? i out combining the two equations above yields: g dc = g mp ? g power 1.7 ? ? v in i out v/v converter efficiency will vary with i out and switching frequency ? osc as shown in the typical performance characteristics curves. output pole: p1 = 2 2 ? ? r l ? c out hz error amplifier pole: p2 = 1 2 ? ? r o ? (c c + c f ) hz error amplifier zero: z1 = 1 2 ? ? r c ? c c hz esr zero: z2 = 1 2 ? ? r esr ? c out hz rhp zero: z3 = v in 2 ? r l 2 ? ? v out 2 ? l hz high frequency pole: p3 > ? osc 3 phase lead zero: z4 = 1 2 ? ? (r1 + r pl ) ? c pl hz phase lead pole: p4 = 1 2 ? ? r1 ? r2 r1 + r2 + r pl ? ? ? ? ? ? ? c pl hz error amplifier filter pole: p5 = 1 2 ? ? r c ? c c ? c f c c + c f ? ? ? ? ? ? hz the current mode zero (z3) is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. as a general rule, the frequency at which the open-loop gain of the converter is reduced to unity, known as the crossover frequency ? c , should be set to less than one third of the right half plane zero (z3), and under one eighth of the switching frequency ? osc . once ? c is selected, the values for the compensation components can be calculated using a bode plot of the power stage or two generally valid assumptions: p1 dominates the gain of the power stage for frequencies lower than ? c and ? c is much higher than p2. first calculate the power stage gain at ? c , g ?c in v/v. assuming the output pole p1 dominates g ?c for this range, it is expressed by: g ?c g dc 1+ ? c p1 ? ? ? ? ? ? 2 v/v decide how much phase margin ( m ) is desired. greater phase margin can offer more stability while lower phase mar - gin can yield faster transient response. typically, m 60 is optimal for minimizing transient response time while allowing sufficient margin to account for component vari- ability. 1 is the phase boost of z1, p2, and p5 while 2 is the phase boost of z5 and p4. select 1 and 2 such that 1 74 ; 2 2 ? tan ? 1 v out 1.2v ? ? ? ? ? ? ? 90 and 1 + 2 = m + tan ? 1 ? c z3 ? ? ? ? ? ? where v out is in v and ? c and z3 are in khz. setting z1, p5, z4, and p4 such that z1 = ? c a 1 , p5 = ? c a 1 , z4 = ? c a 2 , p4 = ? c a 2 allows a 1 and a 2 to be determined using 1 and 2 a 1 = tan 2 1 + 90 2 ? ? ? ? ? ? , a 2 = tan 2 2 + 90 2 ? ? ? ? ? ? a pplica t ions i n f or m a t ion
ltc3122 16 3122f the compensation will force the converter gain g boost to unity at ? c by using the following expression for c c : c c = 10 3 ? g ma ? r2 ? g ?c a 1 ? 1 ( ) a 2 2 ? ? c ? r1 + r2 ( ) a 1 pf (g ma in s, ? c in khz, g ?c in v/v) once c c is calculated, r c and c f are determined by: r c = 10 6 ? a 1 2 ? ? c ? c c k ? (? c in khz, c c in pf) c f = c c a 1 ? 1 the values of the phase lead components are given by the expressions: r pl = r1 ? a 2 ? r1 ? r2 r1 + r2 ? ? ? ? ? ? a 2 ? 1 k ? and c pl = 10 6 a 2 ? 1 ( ) r1 + r2 ( ) 2 ? ? c ? r1 2 a 2 pf where r1, r2, and r pl are in k and ? c is in khz. note that selecting 2 = 0 forces a 2 = 1, and so the converter will have type ii compensation and therefore no feedforward: r pl is open (infinite impedance) and c pl = 0pf. if a 2 = 0.833 ? v out (its maximum), feedforward is maximized; r pl = 0 and c pl is maximized for this com- pensation method. once the compensation values have been calculated, ob- taining a converter bode plot is strongly recommended to verify calculations and adjust values as required. using the circuit in figure 5 as an example, table 3 shows the parameters used to generate the bode plot shown in figure 6. table 3. bode plot parameters for type ii compensation parameter value units comment v in 5 v app specific v out 12 v app specific r l 15 app specific c out 22 f app specific r esr 5 m app specific l 3.3 h app specific ? osc 1 mhz adjustable r1 1020 k adjustable r2 113 k adjustable g ma 95 s fixed r o 10 m fixed g mp 3.4 s fixed 80 % app specific r c 210 k adjustable c c 390 pf adjustable c f 10 pf adjustable r pl 0 k optional c pl 0 pf optional from figure 6, the phase is 60 when the gain reaches 0db, so the phase margin of the converter is 60. the crossover frequency is 15khz, which is more than three times lower than the 108.4khz frequency of the rhp zero to achieve adequate phase margin. a pplica t ions i n f or m a t ion
ltc3122 17 3122f a pplica t ions i n f or m a t ion figure 5. 1mhz, 5v to 12v, 800ma boost converter figure 6. bode plot for example converter transient response with 400ma to 800ma load step switching waveforms with 800ma load 3122 f05a v in sd pwm/sync rt v cc v out cap fb v c ltc3122 sgnd pgnd r c 210k c c 390pf sw l1 3.3h r2 113k r1 1.02m c f 10pf c vcc 4.7f c1 100nf c out 22f v out 12v 800ma r t 57.6k v in 5v c in 4.7f onoff pwm burst 200ns/div 3122 f05b v out 100mv/div ac-coupled sw 10v/div inductor current 1a/div frequency (khz) 0.01 gain (db) phase (deg) 170 150 110 70 50 130 90 30 10 ?10 ?30 180 140 100 60 20 ?20 ?60 ?100 ?140 ?180 ?220 10 0.1 3122 f06 1000 1 100 gain phase 100s/div 3122 f05c v out 500mv/div ac-coupled i load 500ma/div
ltc3122 18 3122f figure 7. boost converter with phase lead figure 8. bode plot showing phase lead 3122 f06 v in sd pwm/sync rt v cc v out cap fb v c ltc3122 sgnd pgnd r c 127k c c 220pf sw l1 3.3h r2 113k 1.02m c f 33pf c vcc 4.7f c1 100nf c out 22f v out 12v 800ma r t 57.6k v in 5v c in 4.7f onoff pwm burst r pl 604k c pl 10pf a pplica t ions i n f or m a t ion the circuit in figure 7 shows the same application as that in figure 5 with type iii compensation. this is ac - complished by adding c pl and r pl and adjusting c c , c f , and r c accordingly. table 4 shows the parameters used to generate the bode plot shown in figure 8. table 4. bode plot parameters for type iii compensation parameter value units comment v in 5 v app specific v out 12 v app specific r l 15 app specific c out 22 f app specific r esr 5 m app specific l 3.3 h app specific ? osc 1 mhz adjustable r1 113 k adjustable r2 1020 k adjustable g ma 95 s fixed r o 10 m fixed g mp 3.4 s fixed 80 % app specific r c 127 k adjustable c c 220 pf adjustable c f 33 pf adjustable r pl 604 k adjustable c pl 10 pf adjustable from figure 8, the phase margin is still optimized at 60 and the crossover frequency remains 15khz. adding c pl and r pl provides some feedforward signal in burst mode operation, leading to lower output voltage ripple. frequency (khz) 0.01 gain (db) phase (deg) 170 150 110 70 50 130 90 30 10 ?10 ?30 180 140 100 60 20 ?20 ?60 ?100 ?140 ?180 ?220 10 0.1 3122 f08 1000 1 100 gain phase
ltc3122 19 3122f typical a pplica t ions single li-cell to 6v, 5w synchronous boost converter for rf transmitter 2 aa cell to 12v synchronous boost converter, 180ma 3122 ta02a v in sd pwm/sync rt v cc v out cap fb v c ltc3122 sgnd pgnd r c 73.2k c c 560pf sw l1 3.3h r2 121k r1 487k c f 47pf c vcc 4.7f c1 100nf c out 22f v out 6v 833ma r t 57.6k v in 2.5v to 4.2v c in 4.7f onoff c in , c vcc : 4.7f, 16v, x7r, 1206 c1: 100nf, 16v, x7r, 1206 c out : 22f, 16v, x7r, 1812 l1: tdk spm6530t-3r3m 3122 ta03a v in sd pwm/sync rt v cc v out cap fb v c ltc3122 sgnd pgnd r c 200k c c 560pf sw l1 3.3h r2 113k r1 1.02m c f 10pf c vcc 4.7f c1 100nf c out 22f v out 12v 180ma r t 57.6k v in 1.8v to 3v c in 4.7f onoff c in , c vcc : 4.7f, 16v, x7r, 1206 c1: 100nf, 16v, x7r, 1206 c out : 22f, 25v, x7r, 1812 l1: tdk spm6530t-3r3m 100s/div 80ma 80ma 833ma 3122 ta02b output current 500ma/div v out 500mv/div ac-coupled v in = 3.6v v in (v) 1.6 input current (a) 2.3 2.1 1.7 1.3 1.1 1.9 1.5 0.9 0.7 0.5 efficiency (%) 100 90 70 50 40 80 60 30 20 10 0 2.2 2.4 2.6 2.8 1.8 3122 ta03b 2 3.23 efficiency input current
ltc3122 20 3122f typical a pplica t ions 3.3v to 12v synchronous boost converter with output disconnect, 500ma usb/battery powered synchronous boost converter, 4.3v to 5v, 1a 3122 ta04a v in sd pwm/sync rt v cc v out cap fb v c ltc3122 sgnd pgnd r c 232k c c 470pf sw l1 3.3h r2 113k r1 1.02m c f 10pf c vcc 4.7f c1 100nf c out 22f v out 12v 500ma r t 57.6k v in 3.3v c in 4.7f onoff c in , c vcc : 4.7f, 16v, x7r, 1206 c1: 100nf, 16v, x7r, 1206 c out : 22f, 25v, x7r, 1812 l1: tdk spm6530t-3r3m 3122 ta05a v in sd pwm/sync rt v cc v out cap fb v c ltc3122 sgnd pgnd r c 43.2k c c 1000pf sw l1 3.3h r2 121k r1 383k c f 68pf c vcc 4.7f c1 100nf c out 100f v out 5v 1a r t 57.6k v in 4.3v to 5.5v c in 4.7f onoff c in , c vcc : 4.7f, 16v, x7r, 1206 c1: 100nf, 16v, x7r, 1206 c out : 100f, 16v, x7r, 1812 l1: tdk spm6530t-3r3m 200s/div 3122 ta05b output current 500ma/div v out 500mv/div ac-coupled v in = 4.3v 100ma 1a 500ns/div 3122 ta04b inductor current 1a/div sw 5v/div
ltc3122 21 3122f typical a pplica t ions 5v to dual output synchronous boost converter, 15v single li-cell 3-led driver, 2.5v/4.2v to 350ma 2ms/div 3122 ta07b led current 100ma/div sd 5v/div v in = 3.6v 3122 ta07a v in sd pwm/sync rt v cc v out cap fb v c ltc3122 sgnd pgnd r c 2k c c 3.9nf sw l1 3.3h c vcc 4.7f v cc c1 100nf lt1006 c out1 22f r t 57.6k v in 2.5v to 4.2v c in 4.7f onoff c in , c vcc : 4.7f, 6v, x7r, 1206 c1: 100nf, 6v, x7r, 1206 c out : 22f, 16v, x7r, 1812 l1: tdk spm6530t-3r3m d1, d2, d3: cree xpgwht-l1-0000-00g51 + ? r1 1.02m r2 30.9k r s 0.1 d1 d2 d3 output current (ma) 0 v out2 (v) ?15.1 ?15.0 ?14.8 ?14.6 ?14.5 ?14.9 ?14.7 ?14.4 ?14.3 ?14.2 ?14.1 v out1 (v) 15.1 15.0 14.8 14.6 14.5 14.9 14.7 14.4 14.3 14.2 14.1 150 50 3122 ta06b 100 200 v out1 v out2 3122 ta06a v in sd pwm/sync rt v cc v out cap fb v c ltc3122 sgnd pgnd r c 365k c c 150pf sw l1 3.3h r2 113k z1 r1 1.3m c f 10pf c vcc 4.7f c1 100nf u1 c2 470nf c out1 22f c out2 47f v out1 15v v out2 ?15v r t 57.6k v in 5v c in 4.7f onoff c in , c vcc : 4.7f, 16v, x7r, 1206 c out2 : 47f, 25v, x7r, 1206 c1: 100nf, 16v, x7r, 1206 c out1 : 22f, 25v, x7r, 1812 c2: 470nf, 25v, x7r, 1206 l1: tdk spm6530t-3r3m u1: central semiconductor cbat54s z1: diodes, inc. ddz16asf-7
ltc3122 22 3122f p ackage descrip t ion de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695 rev d) 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notch r = 0.20 or 0.35 45 chamfer pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (ue12/de12) dfn 0806 rev d 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 3.30 0.10 0.25 0.05 0.50 bsc 1.70 0.05 3.30 0.05 0.50 bsc 0.25 0.05
ltc3122 23 3122f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev f) msop (mse12) 0911 rev f 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail ?b? 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev f)
ltc3122 24 3122f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0712 ? printed in usa r ela t e d p ar t s typical a pplica t ion dual supercapacitor backup power supply, 0.5v to 5v part number description comments LTC3421 3a i sw , 3mhz, synchronous step-up dc/dc converter with output disconnect 95% efficiency, v in = 0.5v to 4.5v, v out(max) = 5.25v, i q = 12a, i sd < 1a, qfn24 package ltc3422 1.5a i sw , 3mhz synchronous step-up dc/dc converter with output disconnect 95% efficiency, v in = 0.5v to 4.5v, v out(max) = 5.25v, i q = 25a, i sd < 1a, 3mm 3mm dfn package ltc3112 2.5a i sw , 750khz, synchronous buck-boost dc/dc converter with output disconnect, burst mode operation 95% efficiency, v in = 2.7v to 15v, v out(max) = 14v, i q = 50a, i sd < 1a, 4mm 5mm dfn and tssop packages ltc3458 1.4a i sw , 1.5mhz, synchronous step-up dc/dc converter/ output disconnect/burst mode operation 93% efficiency, v in = 1.5v to 6v, v out(max) = 7.5v, i q = 15a, i sd < 1a, dfn12 package ltc3528 1a i sw , 1mhz, synchronous step-up dc/dc converter with output disconnect/burst mode operation 94% efficiency, v in = 700mv to 5.25v, v out(max) = 5.25v, i q = 12a, i sd < 1a, 3mm 2mm dfn package ltc3539 2a i sw , 1mhz/2mhz, synchronous step-up dc/dc converters with output disconnect/burst mode operation 94% efficiency, v in = 700mv to 5.25v, v out(max) = 5.25v, i q = 10a, i sd < 1a, 3mm 2mm dfn package ltc3459 70ma i sw , 10v micropower synchronous boost converter/ output disconnect/burst mode operation v in = 1.5v to 5.5v, v out(max) = 10v, i q = 10a, i sd < 1a, thinsot? package ltc3499 750ma synchronous step-up dc/dc converters with reverse-battery protection 94% efficiency, v in = 1.8v to 5.5v, v out(max) = 6v, i q = 20a, i sd < 1a, 3mm 3mm dfn and msop packages ltc3115-1 40v, 2a synchronous buck-boost dc/dc converter 95% efficiency, v in = 2.7v to 40v, v out(max) = 40v, i q = 50a, i sd < 3a, 4mm 5mm dfn and tssop packages 3122 ta08a v in v out ltc3122 sgnd pgnd r c 43.2k c c 1nf sw l1 3.3h r2 121k r1 383k c f 68pf c vcc 4.7f c1 100nf c out 100f v out 5v r t 57.6k v in 0.5v to 5v c in , c vcc : 4.7f, 16v, x7r, 1206 c1: 100nf, 16v, x7r, 1206 c out : 100f, 16v, x7r, 1812 l1: tdk spm6530t-3r3m sc1, sc2: maxwell bcap0050-p270 sd sc1 50f sc2 50f pwm/sync rt v cc cap fb v c onoff c in 4.7f 500ns/div 3122 ta08b sw 5v/div inductor current 500ma/div v out 20mv/div ac-coupled v in = 0.5v output current = 50ma

▲Up To Search▲

Price & Availability of LTC3421

	To Download LTC3421 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .